// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  stlqu_harden_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2018/9/28
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2020/07/07 21:45:40 Create file
// ******************************************************************************

#ifndef STLQU_HARDEN_C_UNION_DEFINE_H
#define STLQU_HARDEN_C_UNION_DEFINE_H

/* Define the union csr_crg_cfg_stlqu_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_ring_stlqu_harden : 2;       /* [1:0] */
        u32 icg_en_cp_stlqu_harden : 1;         /* [2] */
        u32 srst_req_ring_stlqu_harden : 2;     /* [4:3] */
        u32 srst_req_grs_ring_stlqu_harden : 1; /* [5] */
        u32 srst_req_lrs_ring_stlqu_harden : 1; /* [6] */
        u32 srst_req_cp_stlqu_harden : 1;       /* [7] */
        u32 rsv_0 : 24;                         /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_stlqu_harden_u;

/* Define the union csr_rst_cfg_sml0_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_sml_sml0_harden : 1;        /* [0] */
        u32 icg_en_sml_div2_sml0_harden : 1;   /* [1] */
        u32 icg_en_smeg_sml0_harden : 1;       /* [2] */
        u32 icg_en_ring_sml0_harden : 1;       /* [3] */
        u32 srst_req_sml_sml0_harden : 1;      /* [4] */
        u32 srst_req_sml_div2_sml0_harden : 1; /* [5] */
        u32 srst_req_smeg_sml0_harden : 1;     /* [6] */
        u32 srst_req_ring_sml0_harden : 1;     /* [7] */
        u32 rsv_1 : 24;                        /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_sml0_harden_u;

/* Define the union csr_rst_cfg_sml1_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_sml_sml1_harden : 1;        /* [0] */
        u32 icg_en_sml_div2_sml1_harden : 1;   /* [1] */
        u32 icg_en_smeg_sml1_harden : 1;       /* [2] */
        u32 icg_en_ring_sml1_harden : 1;       /* [3] */
        u32 srst_req_sml_sml1_harden : 1;      /* [4] */
        u32 srst_req_sml_div2_sml1_harden : 1; /* [5] */
        u32 srst_req_smeg_sml1_harden : 1;     /* [6] */
        u32 srst_req_ring_sml1_harden : 1;     /* [7] */
        u32 rsv_2 : 24;                        /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_cfg_sml1_harden_u;

/* Define the union csr_ring_sta_sml0_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml0_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_3 : 22;                         /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_sml0_harden_u;

/* Define the union csr_ring_sta_sml1_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml1_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_4 : 22;                         /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_sml1_harden_u;

/* Define the union csr_ring_sta_stlqu_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stlqu_harden_rs_nd_pe_crdt_sta : 10; /* [9:0] */
        u32 rsv_5 : 22;                          /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_stlqu_harden_u;

/* Define the union csr_rst_comb_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 glb_sft_rstn_enable : 1; /* [0] */
        u32 glb_srst_req : 1;        /* [1] */
        u32 rsv_6 : 30;              /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_comb_cfg_0_u;

/* Define the union csr_rst_comb_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 time_wait_efuse_done : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_comb_cfg_1_u;

/* Define the union csr_rst_comb_cfg_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_bypass_icg_en_pll : 1;   /* [0] */
        u32 srst_req_efuse_membst : 12; /* [12:1] */
        u32 rsv_7 : 19;                 /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_comb_cfg_2_u;

/* Define the union csr_pll0_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_cfg0 : 16; /* [15:0] */
        u32 pll0_cfg1 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_0_u;

/* Define the union csr_pll0_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_cfg2 : 16; /* [15:0] */
        u32 pll0_cfg3 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_1_u;

/* Define the union csr_pll0_cfg_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_cfg4 : 16; /* [15:0] */
        u32 pll0_cfg5 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_2_u;

/* Define the union csr_pll0_cfg_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_cfg6 : 16; /* [15:0] */
        u32 pll0_cfg7 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_3_u;

/* Define the union csr_pll0_cfg_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_cfg8 : 16; /* [15:0] */
        u32 pll0_cfg9 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_4_u;

/* Define the union csr_pll0_cfg_5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_cfg10 : 16; /* [15:0] */
        u32 rsv_8 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_5_u;

/* Define the union csr_pll0_cfg_6_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_pllfctrl0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_6_u;

/* Define the union csr_pll0_cfg_7_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_pllfctrl1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_7_u;

/* Define the union csr_pll0_cfg_8_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_bypass_external_n : 1; /* [0] */
        u32 pll0_peri_mode : 1;         /* [1] */
        u32 dll_en_pll0 : 1;            /* [2] */
        u32 probe_mode_pll0 : 1;        /* [3] */
        u32 icg_en_probe_pll0 : 1;      /* [4] */
        u32 rsv_9 : 27;                 /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_cfg_8_u;

/* Define the union csr_pll0_state_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_state0 : 16; /* [15:0] */
        u32 pll0_state1 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_state_0_u;

/* Define the union csr_pll0_state_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pll0_lock : 1; /* [0] */
        u32 rsv_10 : 31;   /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pll0_state_1_u;

/* Define the union csr_sml0_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_iso_en_sml0_harden : 1;        /* [0] */
        u32 sml_mtcmos_pwr_on_sml0_harden : 1; /* [1] */
        u32 srst_req_wol_por_sml0_harden : 1;  /* [2] */
        u32 srst_req_wol_comb_sml0_harden : 1; /* [3] */
        u32 wol_rst_sel_sml0_harden : 1;       /* [4] */
        u32 rsv_11 : 27;                       /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml0_power_cfg_u;

/* Define the union csr_sml0_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_mtcmos_pwr_ack_sml0_harden : 1; /* [0] */
        u32 rsv_12 : 31;                        /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml0_power_ack_u;

/* Define the union csr_sml1_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_iso_en_sml1_harden : 1;        /* [0] */
        u32 sml_mtcmos_pwr_on_sml1_harden : 1; /* [1] */
        u32 srst_req_wol_por_sml1_harden : 1;  /* [2] */
        u32 srst_req_wol_comb_sml1_harden : 1; /* [3] */
        u32 wol_rst_sel_sml1_harden : 1;       /* [4] */
        u32 rsv_13 : 27;                       /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml1_power_cfg_u;

/* Define the union csr_sml1_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sml_mtcmos_pwr_ack_sml1_harden : 1; /* [0] */
        u32 rsv_14 : 31;                        /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_sml1_power_ack_u;

/* Define the union csr_chip_uncrt_err_en_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfqu_uncrt_err_en : 1;    /* [0] */
        u32 pqm_uncrt_err_en : 1;      /* [1] */
        u32 mqm_uncrt_err_en : 1;      /* [2] */
        u32 stlqu_uncrt_err_en : 1;    /* [3] */
        u32 smf0_uncrt_err_en : 1;     /* [4] */
        u32 smf1_uncrt_err_en : 1;     /* [5] */
        u32 smf2_uncrt_err_en : 1;     /* [6] */
        u32 smf3_uncrt_err_en : 1;     /* [7] */
        u32 sml0_uncrt_err_en : 1;     /* [8] */
        u32 sml1_uncrt_err_en : 1;     /* [9] */
        u32 sml2_uncrt_err_en : 1;     /* [10] */
        u32 sml3_uncrt_err_en : 1;     /* [11] */
        u32 stftile0_uncrt_err_en : 1; /* [12] */
        u32 stftile1_uncrt_err_en : 1; /* [13] */
        u32 stftile2_uncrt_err_en : 1; /* [14] */
        u32 stftile3_uncrt_err_en : 1; /* [15] */
        u32 stltile0_uncrt_err_en : 1; /* [16] */
        u32 stltile1_uncrt_err_en : 1; /* [17] */
        u32 stltile2_uncrt_err_en : 1; /* [18] */
        u32 stltile3_uncrt_err_en : 1; /* [19] */
        u32 mpu_uncrt_err_en : 1;      /* [20] */
        u32 cpi_uncrt_err_en : 1;      /* [21] */
        u32 lcam_uncrt_err_en : 1;     /* [22] */
        u32 ipsutx_uncrt_err_en : 1;   /* [23] */
        u32 perx_uncrt_err_en : 1;     /* [24] */
        u32 ipsurx_uncrt_err_en : 1;   /* [25] */
        u32 petx_uncrt_err_en : 1;     /* [26] */
        u32 cpb_uncrt_err_en : 1;      /* [27] */
        u32 ckd_err_int0_en : 1;       /* [28] */
        u32 ckd_err_int1_en : 1;       /* [29] */
        u32 pcie_uncrt_err_en : 1;     /* [30] */
        u32 cryptorx_uncrt_err_en : 1; /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_chip_uncrt_err_en_0_u;

/* Define the union csr_chip_uncrt_err_en_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cryptotx_uncrt_err_en : 1; /* [0] */
        u32 ts_uncrt_err_en : 1;       /* [1] */
        u32 mag_uncrt_err_en : 1;      /* [2] */
        u32 fc_uncrt_err_en : 1;       /* [3] */
        u32 hva_uncrt_err_en : 1;      /* [4] */
        u32 rsv_15 : 27;               /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_chip_uncrt_err_en_1_u;

/* Define the union csr_chip_uncrt_err_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 stfqu_uncrt_err : 1;    /* [0] */
        u32 pqm_uncrt_err : 1;      /* [1] */
        u32 mqm_uncrt_err : 1;      /* [2] */
        u32 stlqu_uncrt_err : 1;    /* [3] */
        u32 smf0_uncrt_err : 1;     /* [4] */
        u32 smf1_uncrt_err : 1;     /* [5] */
        u32 smf2_uncrt_err : 1;     /* [6] */
        u32 smf3_uncrt_err : 1;     /* [7] */
        u32 sml0_uncrt_err : 1;     /* [8] */
        u32 sml1_uncrt_err : 1;     /* [9] */
        u32 sml2_uncrt_err : 1;     /* [10] */
        u32 sml3_uncrt_err : 1;     /* [11] */
        u32 stftile0_uncrt_err : 1; /* [12] */
        u32 stftile1_uncrt_err : 1; /* [13] */
        u32 stftile2_uncrt_err : 1; /* [14] */
        u32 stftile3_uncrt_err : 1; /* [15] */
        u32 stltile0_uncrt_err : 1; /* [16] */
        u32 stltile1_uncrt_err : 1; /* [17] */
        u32 stltile2_uncrt_err : 1; /* [18] */
        u32 stltile3_uncrt_err : 1; /* [19] */
        u32 mpu_uncrt_err : 1;      /* [20] */
        u32 cpi_uncrt_err : 1;      /* [21] */
        u32 lcam_uncrt_err : 1;     /* [22] */
        u32 ipsutx_uncrt_err : 1;   /* [23] */
        u32 perx_uncrt_err : 1;     /* [24] */
        u32 ipsurx_uncrt_err : 1;   /* [25] */
        u32 petx_uncrt_err : 1;     /* [26] */
        u32 cpb_uncrt_err : 1;      /* [27] */
        u32 ckd_err_int0 : 1;       /* [28] */
        u32 ckd_err_int1 : 1;       /* [29] */
        u32 pcie_uncrt_err : 1;     /* [30] */
        u32 cryptorx_uncrt_err : 1; /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_chip_uncrt_err_0_u;

/* Define the union csr_chip_uncrt_err_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cryptotx_uncrt_err : 1; /* [0] */
        u32 ts_uncrt_err : 1;       /* [1] */
        u32 mag_uncrt_err : 1;      /* [2] */
        u32 fc_uncrt_err : 1;       /* [3] */
        u32 hva_uncrt_err : 1;      /* [4] */
        u32 rsv_16 : 27;            /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_chip_uncrt_err_1_u;

/* Define the union csr_pcie_waken_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcie0_waken : 1; /* [0] */
        u32 pcie1_waken : 1; /* [1] */
        u32 pcie2_waken : 1; /* [2] */
        u32 pcie3_waken : 1; /* [3] */
        u32 rsv_17 : 28;     /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie_waken_u;

/* Define the union csr_rst_comb_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 reset_type : 6; /* [5:0] */
        u32 rsv_18 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_rst_comb_status_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_crg_cfg_stlqu_harden_u crg_cfg_stlqu_harden;   /* 0 */
    volatile csr_rst_cfg_sml0_harden_u rst_cfg_sml0_harden;     /* 4 */
    volatile csr_rst_cfg_sml1_harden_u rst_cfg_sml1_harden;     /* 8 */
    volatile csr_ring_sta_sml0_harden_u ring_sta_sml0_harden;   /* C */
    volatile csr_ring_sta_sml1_harden_u ring_sta_sml1_harden;   /* 10 */
    volatile csr_ring_sta_stlqu_harden_u ring_sta_stlqu_harden; /* 14 */
    volatile csr_rst_comb_cfg_0_u rst_comb_cfg_0;               /* 18 */
    volatile csr_rst_comb_cfg_1_u rst_comb_cfg_1;               /* 1C */
    volatile csr_rst_comb_cfg_2_u rst_comb_cfg_2;               /* 20 */
    volatile csr_pll0_cfg_0_u pll0_cfg_0;                       /* 24 */
    volatile csr_pll0_cfg_1_u pll0_cfg_1;                       /* 28 */
    volatile csr_pll0_cfg_2_u pll0_cfg_2;                       /* 2C */
    volatile csr_pll0_cfg_3_u pll0_cfg_3;                       /* 30 */
    volatile csr_pll0_cfg_4_u pll0_cfg_4;                       /* 34 */
    volatile csr_pll0_cfg_5_u pll0_cfg_5;                       /* 38 */
    volatile csr_pll0_cfg_6_u pll0_cfg_6;                       /* 3C */
    volatile csr_pll0_cfg_7_u pll0_cfg_7;                       /* 40 */
    volatile csr_pll0_cfg_8_u pll0_cfg_8;                       /* 44 */
    volatile csr_pll0_state_0_u pll0_state_0;                   /* 48 */
    volatile csr_pll0_state_1_u pll0_state_1;                   /* 4C */
    volatile csr_sml0_power_cfg_u sml0_power_cfg;               /* 50 */
    volatile csr_sml0_power_ack_u sml0_power_ack;               /* 54 */
    volatile csr_sml1_power_cfg_u sml1_power_cfg;               /* 58 */
    volatile csr_sml1_power_ack_u sml1_power_ack;               /* 5C */
    volatile csr_chip_uncrt_err_en_0_u chip_uncrt_err_en_0;     /* 60 */
    volatile csr_chip_uncrt_err_en_1_u chip_uncrt_err_en_1;     /* 64 */
    volatile csr_chip_uncrt_err_0_u chip_uncrt_err_0;           /* 68 */
    volatile csr_chip_uncrt_err_1_u chip_uncrt_err_1;           /* 6C */
    volatile csr_pcie_waken_u pcie_waken;                       /* 70 */
    volatile csr_rst_comb_status_u rst_comb_status;             /* 74 */
} S_stlqu_harden_node_csr_REGS_TYPE;

/* Declare the struct pointor of the module stlqu_harden_node_csr */
extern volatile S_stlqu_harden_node_csr_REGS_TYPE *gopstlqu_harden_node_csrAllReg;

/* Declare the functions that set the member value */
int iSetCRG_CFG_STLQU_HARDEN_icg_en_ring_stlqu_harden(unsigned int uicg_en_ring_stlqu_harden);
int iSetCRG_CFG_STLQU_HARDEN_icg_en_cp_stlqu_harden(unsigned int uicg_en_cp_stlqu_harden);
int iSetCRG_CFG_STLQU_HARDEN_srst_req_ring_stlqu_harden(unsigned int usrst_req_ring_stlqu_harden);
int iSetCRG_CFG_STLQU_HARDEN_srst_req_grs_ring_stlqu_harden(unsigned int usrst_req_grs_ring_stlqu_harden);
int iSetCRG_CFG_STLQU_HARDEN_srst_req_lrs_ring_stlqu_harden(unsigned int usrst_req_lrs_ring_stlqu_harden);
int iSetCRG_CFG_STLQU_HARDEN_srst_req_cp_stlqu_harden(unsigned int usrst_req_cp_stlqu_harden);
int iSetRST_CFG_SML0_HARDEN_icg_en_sml_sml0_harden(unsigned int uicg_en_sml_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_icg_en_sml_div2_sml0_harden(unsigned int uicg_en_sml_div2_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_icg_en_smeg_sml0_harden(unsigned int uicg_en_smeg_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_icg_en_ring_sml0_harden(unsigned int uicg_en_ring_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_srst_req_sml_sml0_harden(unsigned int usrst_req_sml_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_srst_req_sml_div2_sml0_harden(unsigned int usrst_req_sml_div2_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_srst_req_smeg_sml0_harden(unsigned int usrst_req_smeg_sml0_harden);
int iSetRST_CFG_SML0_HARDEN_srst_req_ring_sml0_harden(unsigned int usrst_req_ring_sml0_harden);
int iSetRST_CFG_SML1_HARDEN_icg_en_sml_sml1_harden(unsigned int uicg_en_sml_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_icg_en_sml_div2_sml1_harden(unsigned int uicg_en_sml_div2_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_icg_en_smeg_sml1_harden(unsigned int uicg_en_smeg_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_icg_en_ring_sml1_harden(unsigned int uicg_en_ring_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_srst_req_sml_sml1_harden(unsigned int usrst_req_sml_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_srst_req_sml_div2_sml1_harden(unsigned int usrst_req_sml_div2_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_srst_req_smeg_sml1_harden(unsigned int usrst_req_smeg_sml1_harden);
int iSetRST_CFG_SML1_HARDEN_srst_req_ring_sml1_harden(unsigned int usrst_req_ring_sml1_harden);
int iSetRING_STA_SML0_HARDEN_sml0_harden_rs_nd_pe_crdt_sta(unsigned int usml0_harden_rs_nd_pe_crdt_sta);
int iSetRING_STA_SML1_HARDEN_sml1_harden_rs_nd_pe_crdt_sta(unsigned int usml1_harden_rs_nd_pe_crdt_sta);
int iSetRING_STA_STLQU_HARDEN_stlqu_harden_rs_nd_pe_crdt_sta(unsigned int ustlqu_harden_rs_nd_pe_crdt_sta);
int iSetRST_COMB_CFG_0_glb_sft_rstn_enable(unsigned int uglb_sft_rstn_enable);
int iSetRST_COMB_CFG_0_glb_srst_req(unsigned int uglb_srst_req);
int iSetRST_COMB_CFG_1_time_wait_efuse_done(unsigned int utime_wait_efuse_done);
int iSetRST_COMB_CFG_2_sc_bypass_icg_en_pll(unsigned int usc_bypass_icg_en_pll);
int iSetRST_COMB_CFG_2_srst_req_efuse_membst(unsigned int usrst_req_efuse_membst);
int iSetPLL0_CFG_0_pll0_cfg0(unsigned int upll0_cfg0);
int iSetPLL0_CFG_0_pll0_cfg1(unsigned int upll0_cfg1);
int iSetPLL0_CFG_1_pll0_cfg2(unsigned int upll0_cfg2);
int iSetPLL0_CFG_1_pll0_cfg3(unsigned int upll0_cfg3);
int iSetPLL0_CFG_2_pll0_cfg4(unsigned int upll0_cfg4);
int iSetPLL0_CFG_2_pll0_cfg5(unsigned int upll0_cfg5);
int iSetPLL0_CFG_3_pll0_cfg6(unsigned int upll0_cfg6);
int iSetPLL0_CFG_3_pll0_cfg7(unsigned int upll0_cfg7);
int iSetPLL0_CFG_4_pll0_cfg8(unsigned int upll0_cfg8);
int iSetPLL0_CFG_4_pll0_cfg9(unsigned int upll0_cfg9);
int iSetPLL0_CFG_5_pll0_cfg10(unsigned int upll0_cfg10);
int iSetPLL0_CFG_6_pll0_pllfctrl0(unsigned int upll0_pllfctrl0);
int iSetPLL0_CFG_7_pll0_pllfctrl1(unsigned int upll0_pllfctrl1);
int iSetPLL0_CFG_8_pll0_bypass_external_n(unsigned int upll0_bypass_external_n);
int iSetPLL0_CFG_8_pll0_peri_mode(unsigned int upll0_peri_mode);
int iSetPLL0_CFG_8_dll_en_pll0(unsigned int udll_en_pll0);
int iSetPLL0_CFG_8_probe_mode_pll0(unsigned int uprobe_mode_pll0);
int iSetPLL0_CFG_8_icg_en_probe_pll0(unsigned int uicg_en_probe_pll0);
int iSetPLL0_STATE_0_pll0_state0(unsigned int upll0_state0);
int iSetPLL0_STATE_0_pll0_state1(unsigned int upll0_state1);
int iSetPLL0_STATE_1_pll0_lock(unsigned int upll0_lock);
int iSetSML0_POWER_CFG_sml_iso_en_sml0_harden(unsigned int usml_iso_en_sml0_harden);
int iSetSML0_POWER_CFG_sml_mtcmos_pwr_on_sml0_harden(unsigned int usml_mtcmos_pwr_on_sml0_harden);
int iSetSML0_POWER_CFG_srst_req_wol_por_sml0_harden(unsigned int usrst_req_wol_por_sml0_harden);
int iSetSML0_POWER_CFG_srst_req_wol_comb_sml0_harden(unsigned int usrst_req_wol_comb_sml0_harden);
int iSetSML0_POWER_CFG_wol_rst_sel_sml0_harden(unsigned int uwol_rst_sel_sml0_harden);
int iSetSML0_POWER_ACK_sml_mtcmos_pwr_ack_sml0_harden(unsigned int usml_mtcmos_pwr_ack_sml0_harden);
int iSetSML1_POWER_CFG_sml_iso_en_sml1_harden(unsigned int usml_iso_en_sml1_harden);
int iSetSML1_POWER_CFG_sml_mtcmos_pwr_on_sml1_harden(unsigned int usml_mtcmos_pwr_on_sml1_harden);
int iSetSML1_POWER_CFG_srst_req_wol_por_sml1_harden(unsigned int usrst_req_wol_por_sml1_harden);
int iSetSML1_POWER_CFG_srst_req_wol_comb_sml1_harden(unsigned int usrst_req_wol_comb_sml1_harden);
int iSetSML1_POWER_CFG_wol_rst_sel_sml1_harden(unsigned int uwol_rst_sel_sml1_harden);
int iSetSML1_POWER_ACK_sml_mtcmos_pwr_ack_sml1_harden(unsigned int usml_mtcmos_pwr_ack_sml1_harden);
int iSetCHIP_UNCRT_ERR_EN_0_stfqu_uncrt_err_en(unsigned int ustfqu_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_pqm_uncrt_err_en(unsigned int upqm_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_mqm_uncrt_err_en(unsigned int umqm_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stlqu_uncrt_err_en(unsigned int ustlqu_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_smf0_uncrt_err_en(unsigned int usmf0_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_smf1_uncrt_err_en(unsigned int usmf1_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_smf2_uncrt_err_en(unsigned int usmf2_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_smf3_uncrt_err_en(unsigned int usmf3_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_sml0_uncrt_err_en(unsigned int usml0_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_sml1_uncrt_err_en(unsigned int usml1_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_sml2_uncrt_err_en(unsigned int usml2_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_sml3_uncrt_err_en(unsigned int usml3_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stftile0_uncrt_err_en(unsigned int ustftile0_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stftile1_uncrt_err_en(unsigned int ustftile1_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stftile2_uncrt_err_en(unsigned int ustftile2_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stftile3_uncrt_err_en(unsigned int ustftile3_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stltile0_uncrt_err_en(unsigned int ustltile0_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stltile1_uncrt_err_en(unsigned int ustltile1_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stltile2_uncrt_err_en(unsigned int ustltile2_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_stltile3_uncrt_err_en(unsigned int ustltile3_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_mpu_uncrt_err_en(unsigned int umpu_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_cpi_uncrt_err_en(unsigned int ucpi_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_lcam_uncrt_err_en(unsigned int ulcam_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_ipsutx_uncrt_err_en(unsigned int uipsutx_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_perx_uncrt_err_en(unsigned int uperx_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_ipsurx_uncrt_err_en(unsigned int uipsurx_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_petx_uncrt_err_en(unsigned int upetx_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_cpb_uncrt_err_en(unsigned int ucpb_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_ckd_err_int0_en(unsigned int uckd_err_int0_en);
int iSetCHIP_UNCRT_ERR_EN_0_ckd_err_int1_en(unsigned int uckd_err_int1_en);
int iSetCHIP_UNCRT_ERR_EN_0_pcie_uncrt_err_en(unsigned int upcie_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_0_cryptorx_uncrt_err_en(unsigned int ucryptorx_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_1_cryptotx_uncrt_err_en(unsigned int ucryptotx_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_1_ts_uncrt_err_en(unsigned int uts_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_1_mag_uncrt_err_en(unsigned int umag_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_1_fc_uncrt_err_en(unsigned int ufc_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_EN_1_hva_uncrt_err_en(unsigned int uhva_uncrt_err_en);
int iSetCHIP_UNCRT_ERR_0_stfqu_uncrt_err(unsigned int ustfqu_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_pqm_uncrt_err(unsigned int upqm_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_mqm_uncrt_err(unsigned int umqm_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stlqu_uncrt_err(unsigned int ustlqu_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_smf0_uncrt_err(unsigned int usmf0_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_smf1_uncrt_err(unsigned int usmf1_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_smf2_uncrt_err(unsigned int usmf2_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_smf3_uncrt_err(unsigned int usmf3_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_sml0_uncrt_err(unsigned int usml0_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_sml1_uncrt_err(unsigned int usml1_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_sml2_uncrt_err(unsigned int usml2_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_sml3_uncrt_err(unsigned int usml3_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stftile0_uncrt_err(unsigned int ustftile0_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stftile1_uncrt_err(unsigned int ustftile1_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stftile2_uncrt_err(unsigned int ustftile2_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stftile3_uncrt_err(unsigned int ustftile3_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stltile0_uncrt_err(unsigned int ustltile0_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stltile1_uncrt_err(unsigned int ustltile1_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stltile2_uncrt_err(unsigned int ustltile2_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_stltile3_uncrt_err(unsigned int ustltile3_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_mpu_uncrt_err(unsigned int umpu_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_cpi_uncrt_err(unsigned int ucpi_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_lcam_uncrt_err(unsigned int ulcam_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_ipsutx_uncrt_err(unsigned int uipsutx_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_perx_uncrt_err(unsigned int uperx_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_ipsurx_uncrt_err(unsigned int uipsurx_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_petx_uncrt_err(unsigned int upetx_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_cpb_uncrt_err(unsigned int ucpb_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_ckd_err_int0(unsigned int uckd_err_int0);
int iSetCHIP_UNCRT_ERR_0_ckd_err_int1(unsigned int uckd_err_int1);
int iSetCHIP_UNCRT_ERR_0_pcie_uncrt_err(unsigned int upcie_uncrt_err);
int iSetCHIP_UNCRT_ERR_0_cryptorx_uncrt_err(unsigned int ucryptorx_uncrt_err);
int iSetCHIP_UNCRT_ERR_1_cryptotx_uncrt_err(unsigned int ucryptotx_uncrt_err);
int iSetCHIP_UNCRT_ERR_1_ts_uncrt_err(unsigned int uts_uncrt_err);
int iSetCHIP_UNCRT_ERR_1_mag_uncrt_err(unsigned int umag_uncrt_err);
int iSetCHIP_UNCRT_ERR_1_fc_uncrt_err(unsigned int ufc_uncrt_err);
int iSetCHIP_UNCRT_ERR_1_hva_uncrt_err(unsigned int uhva_uncrt_err);
int iSetPCIE_WAKEN_pcie0_waken(unsigned int upcie0_waken);
int iSetPCIE_WAKEN_pcie1_waken(unsigned int upcie1_waken);
int iSetPCIE_WAKEN_pcie2_waken(unsigned int upcie2_waken);
int iSetPCIE_WAKEN_pcie3_waken(unsigned int upcie3_waken);
int iSetRST_COMB_STATUS_reset_type(unsigned int ureset_type);


#endif // STLQU_HARDEN_C_UNION_DEFINE_H
